index.html
2.67 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
<!doctype html>
<title>CodeMirror: VHDL mode</title>
<meta charset="utf-8" />
<link rel=stylesheet href="../../doc/docs.css">
<link rel="stylesheet" href="../../lib/codemirror.css">
<script src="../../lib/codemirror.js"></script>
<script src="../../addon/edit/matchbrackets.js"></script>
<script src="vhdl.js"></script>
<style type="text/css">
.CodeMirror {
border-top: 1px solid black;
border-bottom: 1px solid black;
}
</style>
<div id=nav>
<a href="http://codemirror.net">
<h1>CodeMirror</h1>
<img id=logo src="../../doc/logo.png">
</a>
<ul>
<li>
<a href="../../index.html">Home</a>
<li>
<a href="../../doc/manual.html">Manual</a>
<li>
<a href="https://github.com/codemirror/codemirror">Code</a>
</ul>
<ul>
<li>
<a href="../index.html">Language modes</a>
<li>
<a class=active href="#">VHDL</a>
</ul>
</div>
<article>
<h2>VHDL mode</h2>
<div>
<textarea id="code" name="code"> LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY tb IS END tb; ARCHITECTURE behavior OF tb IS --Inputs signal a : unsigned(2 downto 0) := (others => '0'); signal b : unsigned(2 downto 0) := (others => '0'); --Outputs
signal a_eq_b : std_logic; signal a_le_b : std_logic; signal a_gt_b : std_logic; signal i,j : integer; BEGIN -- Instantiate the Unit Under Test (UUT) uut: entity work.comparator PORT MAP ( a => a, b => b, a_eq_b => a_eq_b, a_le_b => a_le_b,
a_gt_b => a_gt_b ); -- Stimulus process stim_proc: process begin for i in 0 to 8 loop for j in 0 to 8 loop a
<=t o_unsigned(i,3); --integer to unsigned type conversion b <=t o_unsigned(j,3); wait for 10 ns; end loop; end loop; end process;
END; </textarea>
</div>
<script>
var editor = CodeMirror.fromTextArea(document.getElementById("code"),
{
lineNumbers: true,
matchBrackets: true,
mode:
{
name: "vhdl",
}
});
</script>
<p> Syntax highlighting and indentation for the VHDL language.
<h2>Configuration options:</h2>
<ul>
<li>
<strong>atoms</strong> - List of atom words. Default: "null"</li>
<li>
<strong>hooks</strong> - List of meta hooks. Default: ["`", "$"]</li>
<li>
<strong>multiLineStrings</strong> - Whether multi-line strings are accepted. Default: false</li>
</ul>
</p>
<p>
<strong>MIME types defined:</strong> <code>text/x-vhdl</code>.</p>
</article>